Switch set of bi-directional shift register module

ABSTRACT

A switch set used in a bi-directional shift register circuit includes a plurality of switch devices. Each switch device is controlled by corresponding control signals to switch the direction of the input signal. One of the switch devices includes a first switch unit for transmitting a shift register signal from a previous shift register to a shift register according to a first control signal, a second switch unit for transmitting a shift register signal from a next shift register to the shift register according to a second control signal. The first and the second control signals have the same frequency as the clock signal of the shift register circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of applicant's earlier application Ser. No. 12/061,649, filed Apr. 3, 2008, which is included herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switch set of bi-directional shift register modules, and more particularly, to a switch set of bi-directional shift register modules controlled by clock signals.

2. Description of the Prior Art

FIG. 1 is a diagram illustrating a conventional bi-directional shift register circuit 100. The bi-directional shift register circuit 100 comprises shift register module 110 and switch set 120. The shift register module 110 comprises shift registers SR₁, SR₂, and SR₃. The switch set 120 comprises switch devices SW₁, SW₂, and SW₃. Each of the shift registers SR₁˜SR₃ is a one-to-one shift register. That is, each shift register only receives signal outputted from either the previous shift register or the next shift register as input signal. For example, the shift register SR₂ receives either the shift register signal SRO₁ from the shift register SR₁ or the shift register signal SR₃ from the shift register SR₃. Each of the shift registers SR₁˜SR₃ comprises a first input end I₅, a second input end I₆, and a third input end I₇. The first input end I₅ receives a shift register signal, the second input end I₆ (clock input end) receives a clock signal, and the third input end I₇ (clock input end) receives an inversed clock signal of the clock signal. Each of the shift registers SR₁˜SR₃ samples the received shift register signal and output shift register signal according to the clock signal and the inversed clock signal. The shift register module 110 controls the direction of the transmission of the shift register signals of the shift registers SR₁˜SR₃ by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 110 set to transmit shift register signals in a first direction (the forward direction), each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal CLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK. In this way, the shift register module 110 transmits shift register signals in the first direction. When the shift register module 110 is set to transmit shift register signals in the reverse direction of the forward direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal CLK. In this way, the shift register module 110 transmits shift register signals in the reverse of the first direction.

As shown in FIG. 1, the switch device SW₁ controls the input signal SRI₁ of the shift register SR₁. The switch device SW₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₁₁ and CM₁₂. The control end C₁ of the switch device SW₁ receives the control signal VBD, the control end C₂ of the switch device SW₁ receives the control signal XBD, and the control end C₃ of the switch device SW₁ receives the control signal VBD. The input end I₁ of the switch device SW₁ receives a start signal ST, the input end I₂ of the switch device SW₁ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₁ are both coupled to the input end I₅ of the shift register SR₁ for transmitting the input signal SRI₁ to the shift register SR₁. The switch units CM₁₁ and CM₁₂ can be realized with any components having switch functions, for example, Complementary Metal Oxide Semiconductor (CMOS). The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with N-type Metal Oxide Semiconductor (NMOS) and the other one of the switch units of the CMOS is realized with P-type Metal Oxide Semiconductor (PMOS). As shown in FIG. 1, the first end of the PMOS of the switch unit CM₁₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₁₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₁₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₁₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₁₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₁₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₁₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₁₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₁₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₁₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₁₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₁₂ is coupled to the control end C₃.

The switch device SW₂ controls the input signal SR₁₂ of the shift register SR₂. The switch device SW₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₂₁ and CM₂₂. The control end C₁ of the switch device SW₂ receives the control signal VBD, the control end C₂ of the switch device SW₂ receives the control signal XBD, and the control end C₃ of the switch device SW₂ receives the control signal VBD. The input end I₁ of the switch device SW₂ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₂ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₂ are both coupled to the input end I₅ of the shift register SR₂ for transmitting the input signal SRI₂ to the shift register SR₂. The switch units CM₂, and CM₂₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS transistor is realized with PMOS. As shown in FIG. 1, the first end of the PMOS of the switch unit CM₂₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₂₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₂₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₂₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₂₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₂₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₂₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₂₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₂₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₂₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₂₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₂₂ is coupled to the control end C₃.

The switch device SW₃ controls the input signal SRI3 of the shift register SR₃. The switch device SW₃ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₃₁ and CM₃₂. The control end C₁ of the switch device SW₃ receives the control signal VBD, the control end C₂ of the switch device SW₃ receives the control signal XBD, and the control end C₃ of the switch device SW₃ receives the control signal VBD. The input end I₁ of the switch device SW₃ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₃ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₃ are both coupled to the input end I₅ of the shift register SR₃ for transmitting the input signal SRI₃ to the shift register SR₃. The switch units CM₃₁ and CM₃₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS transistor is realized with PMOS. As shown in FIG. 1, the first end of the PMOS of the switch unit CM₃₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₃₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₃₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₃₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₃₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₃₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₃₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₃₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₃₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₃₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₃₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₃₂ is coupled to the control end C₃.

When the shift register circuit 100 is set to operate in the forward direction, the control signal VBD of the switch set 120 is set at a first predetermined voltage (for example, high voltage), and the control signal XBD of the switch set 120 is set a second predetermined voltage (for example, low voltage). In this way, the switch unit CM, of the switch device SW₁ is turned on, the switch unit CM₁₂ of the switch device SW₁ is turned off, and consequently the start signal ST is transmitted to the input end I₅ of the shift register SR₁ as the input signal SRI₁. The switch unit CM₂₁ of the switch device SW₂ is turned on, the switch unit CM₂₂ of the switch device SW₂ is turned off, and consequently the shift register signal SRO₁ is transmitted to the input end I₅ of the shift register SR₂ as the input signal SRI₂. The switch unit CM₃₁ of the switch device SW₃ is turned on, the switch unit CM₃₂ of the switch device SW₃ is turned off, and consequently the shift register signal SRO₂ is transmitted to the input end I₅ of the shift register SR₃ as the input signal SRI₃.

On the other hand, when the shift register circuit 100 is set to operate in the reverse direction, the control signal VBD of the switch set 120 is set at the second predetermined voltage, and the control signal XBD of the switch set 120 is set at the first predetermined voltage. In this way, the switch unit CM₁₂ of the switch device SW₁ is turned on, the switch unit CM₁₁ of the switch device SW₁ is turned off, and consequently the shift register signal SRO₂ is transmitted to the input end I₅ of the shift register SR₁ as the input signal SRI₁. The switch unit CM₂₂ of the switch device SW₂ is turned on, the switch unit CM₂₁ of the switch device SW₂ is turned off, and consequently the shift register signal SRO₃ is transmitted to the input end I₅ of the shift register SR₂ as the input signal SRI₂. The switch unit CM₃₂ of the switch device SW₃ is turned on, the switch unit CM₃₁ of the switch device SW₃ is turned off, and consequently the start signal ST is transmitted to the input end I₅ of the shift register SR₃ as the input signal SRI₃.

The drawback of the conventional switch set 120 is that the control signals VBD and XBD have to respectively keep at the first predetermined voltage and the second predetermined voltage when the shift register circuit 100 is set to operate in the forward direction, and the control signals VBD and XBD have to respectively keep at the second predetermined voltage and the first predetermined voltage when the shift register circuit 100 is set to operate in the reverse direction. Due to the control signals VBD and XBD have to keep at a fixed predetermined voltage for long time, consequently, the stay of the control signals VBD and XBD causes aging of the switch components, which reduce the lifetime of the switch components, especially when the switch components are amorphous silicon (a-Si) thin film transistor(TFT).

FIG. 2 is a diagram illustrating another conventional bi-directional shift register circuit 200. The bi-directional shift register circuit 200 comprises shift register module 210 and switch set 220. The shift register module 210 comprises shift registers SR₁, SR₂, and SR₃. The switch set 220 comprises switch devices SW₁₁, SW₁₂, SW₂₁, SW₂₂, SW₃₁, and SW₃₂. Each of the shift registers SR₁˜SR₃ is a two-to-one shift register. That is, each shift register receives signals outputted both from the previous shift register and the next shift register as input signals. For example, the shift register SR₂ receives both of the shift register signal SRO₁ from the shift register SR₁ and the shift register signal SRO₃ from the shift register SR₃. Each of the shift registers SR₁˜SR₃ comprises a first input end I₅, a second input end I₆, a third input end I₇, and a fourth input end I₈. The first input end I₅ receives a shift register signal, the second input end I₆ (clock input end) receives a clock signal, the third input end I₇ (clock input end) receives the inversed clock signal of the clock signal, and the fourth input end I₈ receives another shift register signal. Each of the shift registers SR₁˜SR₃ samples the received shift register signals and is triggered to output shift register signals according to the clock signal and the inversed clock signal of the clock signal. The shift register module 210 controls the direction of the transmission of the shift register signals of the shift registers SR₁˜SR₃ by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 110 is set to transmit shift register signals in the forward direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal CLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK. In this way, the shift register module 210 transmits shift register signals in the forward direction. When the shift register module 210 is set to transmit shift register signals in the reverse direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal CLK. In this way, the shift register module 210 transmits shift register signals in the reverse direction.

As shown in FIG. 2, the switch device SW₁₁ controls the input signal SRI₁₁ of the shift register SR₁. The switch device SW₁₂ controls the input signal SRI₁₂ of the shift register SR₁. The switch device SW₁₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₁₁ and CM₁₂. The control end C₁ of the switch device SW₁₁ receives the control signal VBD, the control end C₂ of the switch device SW₁₁ receives the control signal XBD, and the control end C₃ of the switch device SW₁₁ receives the control signal VBD. The input end I₁ of the switch device SW₁₁ receives the start signal ST, the input end I₂ of the switch device SW₁₁ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₁₁ are both coupled to the first input end I₅ of the shift register SR₁ for transmitting signals to the shift register SR₁ as the input signals SRI₁₁. The switch units CM₁₁ and CM₁₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₁₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₁₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₁₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₁₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₁₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₁₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₁₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₁₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₁₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₁₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₁₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₁₂ is coupled to the control end C₃.

The switch device SW₁₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₁₃ and CM₁₄. The control end C₁ of the switch SW₁₂ receives the control signal XBD, the control end C₂ of the switch SW₁₂ receives the control signal VBD, and the control end C₃ of the switch SW₁₂ receives the control signal XBD. The input end I₁ of the switch device SW₁₂ receives the start signal ST, the input end I₂ of the switch device SW₁₂ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₁₂ are both coupled to the second input end I₈ of the shift register SR₁ for transmitting signals to the shift register SR₂ as the input signal SRI₁₂. The switch units CM₁₃ and CM₁₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₁₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₁₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₁₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₁₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₁₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₁₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₁₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₁₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₁₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₁₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₁₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₁₄ is coupled to the control end C₃.

The switch device SW₂₁ controls the input signal SRI₂₁ of the shift register SR₂. The switch device SW₂₂ controls the input signal SRI₂₂ of the shift register SR₂. The switch device SW₂₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₂₁ and CM₂₂. The control end C₁ of the switch device SW₂₁ receives the control signal VBD, the control end C₂ of the switch device SW₂₁ receives the control signal XBD, and the control end C₃ of the switch device SW₂₁ receives the control signal VBD. The input end I₁ of the switch device SW₂₁ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₂₁ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₂₁ are both coupled to the first input end I₅ of the shift register SR₂ for transmitting signals to the shift register SR₂ as the input signals SRI₂₁. The switch units CM₂₁ and CM₂₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₂, is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₂, is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₂₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₂₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₂₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₂₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₂₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₂₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₂₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₂₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₂₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₂₂ is coupled to the control end C₃.

The switch device SW₂₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₂₃ and CM₂₄. The control end C₁ of the switch SW₂₂ receives the control signal XBD, the control end C₂ of the switch SW₂₂ receives the control signal VBD, and the control end C₃ of the switch SW₂₂ receives the control signal XBD. The input end I₁ of the switch device SW₂₂ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₂₂ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₂₂ are both coupled to the second input end I₈ of the shift register SR₂ for transmitting signals to the shift register SR₂ as the input signal SRI₁₂. The switch units CM₂₃ and CM₂₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₂₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₂₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₂₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₂₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₂₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₂₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₂₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₂₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₂₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₂₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₂₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₂₄ is coupled to the control end C₃.

The switch device SW₃₁ controls the input signal SRI₃₁ of the shift register SR₃. The switch device SW₃₂ controls the input signal SRI₃₂ of the shift register SR₃. The switch device SW₃₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₃₁ and CM₃₂. The control end C₁ of the switch device SW₃₁ receives the control signal VBD, the control end C₂ of the switch device SW₃₁ receives the control signal XBD, and the control end C₃ of the switch device SW₃₁ receives the control signal VBD. The input end I₁ of the switch device SW₃₁ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₃₁ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₃₁ are both coupled to the first input end I₅ of the shift register SR₃ for transmitting signals to the shift register SR₃ as the input signals SRI₃₁. The switch units CM₃₁ and CM₃₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₃, is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₃, is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₃₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₃₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₃₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₃₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₃₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₃₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₃₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₃₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₃₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₃₂ is coupled to the control end C₃.

The switch device SW₃₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₃₃ and CM₃₄. The control end C₁ of the switch device SW₃₂ receives the control signal XBD, the control end C₂ of the switch SW₃₂ receives the control signal VBD, and the control end C₃ of the switch SW₃₂ receives the control signal XBD. The input end I₁ of the switch device SW₃₂ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₃₂ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₃₂ are both coupled to the second input end I₈ of the shift register SR₃ for transmitting signals to the shift register SR₃ as the input signal SRI₃₂. The switch units CM₃₃ and CM₃₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM₃₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₃₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₃₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₃₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₃₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₃₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₃₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₃₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₃₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₃₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₃₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₃₄ is coupled to the control end C₃.

When the shift register circuit 200 is set to operate in the forward direction, the control signal VBD of the switch set 220 is set at a first predetermined voltage (for example, high voltage), and the control signal XBD of the switch set 220 is set a second predetermined voltage (for example, low voltage). In this way, the switch unit CM₁₁ of the switch device SW₁₁ is turned on, the switch unit CM₁₂ of the switch device SW₁₁ is turned off, and consequently the start signal ST is transmitted to the first input end I₅ of the shift register SR₁ as the input signal SRI₁₁; the switch unit CM₁₄ of the switch device SW₁₂ is turned on, the switch unit CM₁₃ of the switch device SW₁₂ is turned off, and consequently the shift register signal SRO₂ is transmitted to the second input end I₈ of the shift register SR₁ as the input signal SRI₁₂. The switch unit CM₂₁ of the switch device SW₂₁ is turned on, the switch unit CM₂₂ of the switch device SW₂₁ is turned off, and consequently the shift register signal SRO₁ is transmitted to the first input end I₅ of the shift register SR₂ as the input signal SRI₂₁; the switch unit CM₂₄ of the switch device SW₂₂ is turned on, the switch unit CM₂₃ of the switch device SW₂₂ is turned off, and consequently the shift register signal SRO₃ is transmitted to the second input end I₈ of the shift register SR₂ as the input signal SRI₂₂. The switch unit CM₃₁ of the switch device SW₃₁ is turned on, the switch unit CM₃₂ of the switch device SW₃₁ is turned off, and consequently the shift register signal SRO₂ is transmitted to the first input end I₅ of the shift register SR₃ as the input signal SRI₃₁; the switch unit CM₃₄ of the switch device SW₃₂ is turned on, the switch unit CM₃₃ of the switch device SW₃₂ is turned off, and consequently the start signal ST is transmitted to the second input end I₈ of the shift register SR₃ as the input signal SRI₃₂.

On the other hand, when the shift register circuit 200 is set to operate in the reverse direction, the control signal VBD of the switch set 220 is set at the second predetermined voltage, and the control signal XBD of the switch set 220 is set at the first predetermined voltage. In this way, the switch unit CM₁₂ of the switch device SW₁₁ is turned on, the switch unit CM₁₁ of the switch device SW₁₁ is turned off, and consequently the shift register signal SRO₂ is transmitted to the first input end I₅ of the shift register SR₁ as the input signal SRI₁₁; the switch unit CM₁₃ of the switch device SW₁₂ is turned on, the switch unit CM₁₄ of the switch device SW₁₂ is turned off, and consequently the start signal ST is transmitted to the second input end I₈ of the shift register SR₁ as the input signal SRI₁₂. The switch unit CM₂₂ of the switch device SW₂₁ is turned on, the switch unit CM₂₁ of the switch device SW₂₁ is turned off, and consequently the shift register signal SRO₃ is transmitted to the first input end I₅ of the shift register SR₂ as the input signal SRI₂₁; the switch unit CM₂₃ of the switch device SW₂₂ is turned on, the switch unit CM₂₄ of the switch device SW₂₂ is turned off, and consequently the shift register signal SRO₁ is transmitted to the second input end I₈ of the shift register SR₂ as the input signal SRI₂₂. The switch unit CM₃₂ of the switch device SW₃₁ is turned on, the switch unit CM₃₁ of the switch device SW₃₁ is turned off, and consequently the start signal ST is transmitted to the first input end I₅ of the shift register SR₃ as the input signal SRI₃₁; the switch unit CM₃₃ of the switch device SW₃₂ is turned on, the switch unit CM₃₄ of the switch device SW₃₂ is turned off, and consequently the shift register signal SRO₂ is transmitted to the second input end I₈ of the shift register SR₃ as the input signal SRI₃₂.

The drawback of the conventional switch set 220 is that the control signals VBD and XBD have to respectively keep at the first predetermined voltage and the second predetermined voltage when the shift register circuit 200 is set to operate in the forward direction, and the control signals VBD and XBD have to respectively keep at the second predetermined voltage and the first predetermined voltage when the shift register circuit 200 is set to operate in the reverse direction. Due to the control signals VBD and XBD have to keep at a fixed predetermined voltage for long time, the fixed voltage will cause aging of the switch components, which in turn reduces the lifetime of the switch components, especially when the switch components are amorphous silicon (a-Si) thin film transistors (TFTs).

SUMMARY OF THE INVENTION

The present invention provides a switch set of a bi-directional shift register module. The shift register module comprises a first shift register, a second shift register, and a third shift register. The second shift register is coupled to the first shift register. The third shift register is coupled to the second shift register. The shift register module sequentially transmits shift register signals according to a first clock signal and an inversed clock signal of the first clock signal. The switch set comprises a first switch device, a second switch device, a third switch device, and a fourth switch device. The first switch device comprises a first control end for receiving a second clock signal, a second control end for receiving an inversed clock signal of the second clock signal, a third control end for receiving the second clock signal, a first input end for receiving a start signal, a second input end coupled to an output end of the second shift register, a first output end coupled to an input end of the first shift register for coupling the first input end of the first switch device to the first input end of the first shift register when the second clock signal is at a first predetermined voltage, and a second output end coupled to the input end of the first shift register for coupling the second input end of the first switch device to the first input end of the first shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage. The second switch device comprises a first control end for receiving the inversed clock signal of the second clock signal, a second control end for receiving the second clock signal, a third control end for receiving the inversed clock signal of the second clock signal, a first input end for receiving the start signal, a second input end coupled to an output end of the second shift register, a first output end coupled to an second input end of the first shift register for coupling the first input end of the second switch device to the second input end of the first shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage, and a second output end coupled to the second input end of the first shift register for coupling the second input end of the second switch device to the second input end of the first shift register when the second clock signal is at the first predetermined voltage. The third switch device comprises a first control end for receiving the inversed clock signal of the second clock signal, a second control for receiving the second clock signal, a third control for receiving the inversed clock signal of the second clock signal, a first input end coupled to an output end of the first shift register, a second input end coupled to an output end of the third shift register, a first output end coupled to a first input end of the second shift register for coupling the first input end of the third switch device to the first input end of the second shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage, and a second output end coupled to the first input end of the second shift register for coupling the second input end of the third switch device to the first input end of the second shift register when the second clock signal is at the first predetermined voltage. The fourth switch device comprises a first control end for receiving the second clock signal, a second control end for receiving the inversed clock signal of the second clock signal, a third control end for receiving the second clock signal, a first input end coupled to the output end of the first shift register, a second input end coupled to the output end of the third shift register, a first output end coupled to a second input end of the second shift register for coupling the first input end of the fourth switch device to the second end of the second shift register when the second clock signal is at the first predetermined voltage, and a second output end coupled to the second input end of the second shift register for coupling the second input end of the fourth switch device to the second input end of the second shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a conventional bi-directional shift register circuit.

FIG. 2 is a diagram illustrating another conventional bi-directional shift register circuit.

FIG. 3 is a diagram illustrating a first embodiment of the bi-directional shift register circuit of the present invention.

FIG. 4 is a timing diagram of a shift register circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a second embodiment of the bi-directional shift register circuit of the present invention.

FIG. 6 is a timing diagram of a shift register circuit according to the second embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 3 is a diagram illustrating a first embodiment of the bi-directional shift register circuit 300 of the present invention. The bi-directional shift register circuit 300 comprises shift register module 310 and switch set 320. The shift register module 310 comprises shift registers SR₁, SR₂, and SR₃. The switch set 320 comprises switch devices SW₄, SW₅, and SW₆. Each of the shift registers SR₁˜SR₃ is a one-to-one shift register. That is, each shift register only receives signals outputted from either the previous shift register or the next shift register as input signals. For example, the shift register SR₂ receives either the shift register signal SRO₁ from the shift register SR₁ or the shift register signal SRO3 from the shift register SR₃. Each of the shift registers SR₁˜SR₃ comprises a first input end I₅, a second input end I₆, and a third input end I₇. The first input end I₅ receives a shift register signal, the second input end I₆ (clock input end) receives a clock signal, and the third input end I₇ (clock input end) receives an inversed clock signal of the clock signal. Each of the shift registers SR₁˜SR₃ samples the received shift register signal and is triggered to output shift register signals according to the clock signal and the inversed clock signal of the clock signal. The shift register module 310 controls the direction of the transmission of the shift register signals of the shift registers SR₁˜SR₃ by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 310 is set to transmit shift register signals in a first direction (the forward direction), each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal CLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK. In this way, the shift register module 310 transmits shift register signals in the first direction. When the shift register module 310 is set to transmit shift register signals in the reverse direction of the forward direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal CLK. In this way, the shift register module 310 transmits shift register signals in the reverse of the first direction.

The switch device SW₄ controls the input signal SRI₁ of the shift register SR₁. The switch device SW₄ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₄₁ and CM₄₂. The control end C₁ of the switch device SW₄ receives the control signal VBD_(CLK), the control end C₂ of the switch device SW₄ receives the control signal XBD_(CLK), and the control end C₃ of the switch device SW₄ receives the control signal VBD_(CLK). The input end I₁ of the switch device SW₄ receives a start signal ST, the input end I₂ of the switch device SW₄ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₄ are both coupled to the input end I₅ of the shift register SR₁ for transmitting the input signal SRI₁ to the shift register SR₁. The switch units CM₄₁ and CM₄₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 3, the first end of the PMOS of the switch unit CM₄₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₄₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₄₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₄₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₄, is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₄₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₄₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₄₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₄₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₄₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₄₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₄₂ is coupled to the control end C₃.

The switch device SW₅ controls the input signal SRI₂ of the shift register SR₂. The switch device SW₅ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₅₁ and CM₅₂. The control end C₁ of the switch device SW₅ receives the control signal XBD_(CLK), the control end C₂ of the switch device SW₅ receives the control signal VBD_(CLK), and the control end C₃ of the switch device SW₅ receives the control signal XBD_(CLK). The input end I₁ of the switch device SW₅ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₅ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₅ are both coupled to the input end I₅ of the shift register SR₂ for transmitting the input signal SRI₂ to the shift register SR₂. The switch units CM₅₁ and CM₅₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 3, the first end of the PMOS of the switch unit CM₅₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₅₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₅₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₅₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₅₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₅₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₅₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₅₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₅₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₅₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₅₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₅₂ is coupled to the control end C₃.

The switch device SW₆ controls the input signal SRI₃ of the shift register SR₃. The switch device SW₆ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₆₁ and CM₆₂. The control end C₁ of the switch device SW₆ receives the control signal VBD_(CLK), the control end C₂ of the switch device SW₆ receives the control signal XBD_(CLK), and the control end C₃ of the switch device SW₆ receives the control signal VBD_(CLK). The input end I₁ of the switch device SW₆ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₆ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₆ are both coupled to the input end I₅ of the shift register SR₃ for transmitting the input signal SRI₃ to the shift register SR₃. The switch units CM₆₁ and CM₆₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 3, the first end of the PMOS of the switch unit CM₆₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₆₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₆₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₆₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₆, is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₆₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₆₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₆₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₆₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₆₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₆₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₆₂ is coupled to the control end C₃.

In the preferred embodiment, it is noticeable that the control signals VBD_(CLK) and XBD_(CLK) have opposite polarity and have the same frequency as the clock signal CLK. Additionally, the duty ratio of the control signals VBD_(CLK) and XBD_(CLK) are adjustable as desired. When the shift register circuit 300 is changed from the forward direction to the reverse direction or from the reverse direction to the forward direction, the control signals VBD_(CLK) and XBD_(CLK) remain the same and only the phases of the clock signals CLK and XCLK change.

FIG. 4 is a timing diagram of the shift register circuit 300 of the first embodiment of the present invention. As shown in FIG. 4, there is a phase difference D between the control signals VBD_(CLK) and XBD_(CLK) and the clock signals CLK and XCLK. The phase difference D is disposed for ensuring the sampling of the shift register from the input signals is valid. Assuming in the forward direction, each of the shift registers SR₁˜SR₃ respectively samples the input signals SRI₁˜SRI₃ at the falling edges of the clock signal CLK, and stops outputting shift register signals SRO₁˜SRO₃ at the rising clock signal XCLK. Thus, as for the shift register SR₁, when the start signal ST is input, the control signal VBD_(CLK) is at the low voltage (while the control signal XBD_(CLK) is at the high voltage), which turns on the switch unit CM₄₁, turns off the switch unit CM₄₂, and thus the start signal ST is served as the input signal SRI₁. As for the shift register SR₂, when the shift register signal SRO₁ is input, the control signal XBD_(CLK) is at the low voltage (while the control signal VBD_(CLK) is at the high voltage), which turns on the switch unit CM₅₁, turns off the switch unit CM₅₂, and thus the shift register signal SRO₁ is served as the input signal SRI₂. As for the shift register SR₃, when the shift register signal SRO₂ is input, the control signal VBD_(CLK) is at the low voltage (while the control signal XBD_(CLK) is at the high voltage), which turns on the switch unit CM₆₁, turns off the switch unit CM₆₂, and thus the shift register signal SRO₂ is served as the input signal SRI₃. In this way, the transmission of the shift register signals in the forward direction is achieved by utilizing the phases of the clock signals CLK and XCLK. The operation of the transmission of the shift register signals in the reverse direction is similar and is omitted.

FIG. 5 is a diagram illustrating a second embodiment of the bi-directional shift register circuit 500 of the present invention. The bi-directional shift register circuit 500 comprises shift register module 510 and switch set 520. The shift register module 510 comprises shift registers SR₁, SR₂, and SR₃. The switch set 520 comprises switch devices SW₄₁, SW₄₂, SW₅₁, SW₅₂, SW₆₁, and SW₆₂. Each of the shift registers SR₁˜SR₃ is a two-to-one shift register. That is, each shift register receives signals outputted both from the previous shift register and the next shift register as input signals. For example, the shift register SR₂ receives both of the shift register signal SRO₁ from the shift register SR₁ and the shift register signal SRO₃ from the shift register SR₃. Each of the shift registers SR₁˜SR₃ comprises a first input end I₅, a second input end I₆, a third input end I₇, and a fourth input end I₈. The first input end I₅ receives a shift register signal, the second input end I₆ (clock input end) receives a clock signal, the third input end I₇ (clock input end) receives the inversed clock signal of the clock signal, and the fourth input end I₈ receives another shift register signal. Each of the shift registers SR₁˜SR₃ samples the received shift register signals and is triggered to output shift register signals according to the clock signal and the inversed clock signal of the clock signal. The shift register module 510 controls the direction of the transmission of the shift register signals of the shift registers SR₁˜SR₃ by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 510 is set to transmit shift register signals at the forward direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal CLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK. In this way, the shift register module 510 transmits shift register signals in the forward direction. When the shift register module 510 is set to transmit shift register signals in the reverse direction, each second input end I₆ of the shift registers SR₁˜SR₃ is input with the clock signal XCLK, and each third input end I₇ of the shift registers SR₁˜SR₃ is input with the clock signal CLK. In this way, the shift register module 510 transmits shift register signals in the reverse direction.

The switch device SW₄₁ controls the input signal SRI₁₁ of the shift register SR₁. The switch device SW₄₂ controls the input signal SRI₁₂ of the shift register SR₁. The switch device SW₄₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₄₁ and CM₄₂. The control end C₁ of the switch device SW₄₁ receives the control signal VBD_(CLK), the control end C₂ of the switch device SW₄₁ receives the control signal XBD_(CLK), and the control end C₃ of the switch device SW₄₁ receives the control signal VBD_(CLK). The input end I₁ of the switch device SW₄₁ receives the start signal ST, the input end I₂ of the switch device SW₄₁ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₄₁ are both coupled to the first input end I₅ of the shift register SR₁ for transmitting signals to the shift register SR₁ as the input signals SRI₁₁. The switch units CM₄₁ and CM₄₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₄, is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₄, is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₄₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₄₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₄₁ is coupled to the output end I₁, and the control end of the NMOS of the switch unit CM₄₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₄₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₄₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₄₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₄₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₄₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₄₂ is coupled to the control end C₃.

The switch device SW₄₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₄₃ and CM₄₄. The control end C₁ of the switch device SW₄₂ receives the control signal XBD_(CLK), the control end C₂ of the switch device SW₄₂ receives the control signal VBD_(CLK), and the control end C₃ of the switch device SW₄₂ receives the control signal XBD_(CLK). The input end I₁ of the switch device SW₄₂ receives the start signal ST, the input end I₂ of the switch device SW₄₂ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂. The output ends O₁ and O₂ of the switch device SW₄₂ are both coupled to the second input end I₈ of the shift register SR₁ for transmitting signals to the shift register SR₂ as the input signal SRI₁₂. The switch units CM₄₃ and CM₄₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₄₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₄₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₄₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₄₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₄₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₄₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₄₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₄₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₄₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₄₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₄₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₄₄ is coupled to the control end C₃.

The switch device SW₅₁ controls the input signal SRI₂₁ of the shift register SR₂. The switch device SW₅₂ controls the input signal SRI₂₂ of the shift register SR₂. The switch device SW₅₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₅₁ and CM₅₂. The control end C₁ of the switch device SW₅₁ receives the control signal XBD_(CLK), the control end C₂ of the switch device SW₅₁ receives the control signal VBD_(CLK), and the control end C₃ of the switch device SW₅₁ receives the control signal XBD_(CLK). The input end I₁ of the switch device SW₅₁ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₅₁ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₅₁ are both coupled to the first input end I₅ of the shift register SR₂ for transmitting signals to the shift register SR₂ as the input signals SRI₂₁. The switch units CM₅₁ and CM₅₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₅₁ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₅₁ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₅₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₅, is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₅, is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₅₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₅₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₅₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₅₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₅₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₅₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₅₂ is coupled to the control end C₃.

The switch device SW₅₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₅₃ and CM₅₄. The control end C₁ of the switch device SW₅₂ receives the control signal VBD_(CLK), the control end C₂ of the switch device SW₅₂ receives the control signal XBD_(CLK), and the control end C₃ of the switch device SW₅₂ receives the control signal VBD_(CLK). The input end I₁ of the switch device SW₅₂ is coupled to the output end O₃ of the shift register SR₁ for receiving the shift register signal SRO₁, the input end I₂ of the switch device SW₅₂ is coupled to the output end O₃ of the shift register SR₃ for receiving the shift register signal SRO₃. The output ends O₁ and O₂ of the switch device SW₅₂ are both coupled to the second input end I₈ of the shift register SR₂ for transmitting signals to the shift register SR₂ as the input signal SRI₁₂. The switch units CM₅₃ and CM₅₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₅₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₅₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₅₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₅₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₅₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₅₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₅₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₅₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₅₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₅₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₅₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₅₄ is coupled to the control end C₃.

The switch device SW₆₁ controls the input signal SRI₃₁ of the shift register SR₃. The switch device SW₆₂ controls the input signal SRI₃₂ of the shift register SR₃. The switch device SW₆₁ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₆₁ and CM₆₂. The control end C₁ of the switch device SW₆₁ receives the control signal VBD_(CLK), the control end C₂ of the switch device SW₆₁ receives the control signal XBD_(CLK), and the control end C₃ of the switch device SW₆₁ receives the control signal VBD_(CLK). The input end I₁ of the switch device SW₆₁ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₆₁ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₆₁ are both coupled to the first input end I₅ of the shift register SR₃ for transmitting signals to the shift register SR₃ as the input signals SRI₃₁. The switch units CM₆₁ and CM₆₂ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₆, is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₆, is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₆₁ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₆₁ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₆₁ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₆₁ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₆₂ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₆₂ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₆₂ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₆₂ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₆₂ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₆₂ is coupled to the control end C₃.

The switch device SW₆₂ comprises three control ends C₁, C₂, and C₃, two input ends I₁, and I₂, two output ends O₁, and O₂, and two switch units CM₆₃ and CM₆₄. The control end C₁ of the switch device SW₆₂ receives the control signal XBD_(CLK), the control end C₂ of the switch device SW₆₂ receives the control signal VBD_(CLK), and the control end C₃ of the switch device SW₆₂ receives the control signal XBD_(CLK). The input end I₁ of the switch device SW₆₂ is coupled to the output end O₃ of the shift register SR₂ for receiving the shift register signal SRO₂, the input end I₂ of the switch device SW₆₂ receives the start signal ST. The output ends O₁ and O₂ of the switch device SW₆₂ are both coupled to the second input end I₈ of the shift register SR₃ for transmitting signals to the shift register SR₃ as the input signal SRI₃₂. The switch units CM₆₃ and CM₆₄ can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 5, the first end of the PMOS of the switch unit CM₆₃ is coupled to the input end I₁, the second end of the PMOS of the switch unit CM₆₃ is coupled to the output end O₁, and the control end of the PMOS of the switch unit CM₆₃ is coupled to the control end C₁. The first end of the NMOS of the switch unit CM₆₃ is coupled to the input end I₁, the second end of the NMOS of the switch unit CM₆₃ is coupled to the output end O₁, and the control end of the NMOS of the switch unit CM₆₃ is coupled to the control end C₂. The first end of the PMOS of the switch unit CM₆₄ is coupled to the input end I₂, the second end of the PMOS of the switch unit CM₆₄ is coupled to the output end O₂, and the control end of the PMOS of the switch unit CM₆₄ is coupled to the control end C₂. The first end of the NMOS of the switch unit CM₆₄ is coupled to the input end I₂, the second end of the NMOS of the switch unit CM₆₄ is coupled to the output end O₂, and the control end of the NMOS of the switch unit CM₆₄ is coupled to the control end C₃.

In the preferred embodiment, it is noticeable that the control signals VBD_(CLK) and XBD_(CLK) have opposite polarity and have the same frequency as the clock signal CLK. Additionally, the duty ratio of the control signals VBD_(CLK) and XBD_(CLK) are adjustable as desired. When the shift register circuit 500 is changed from the forward direction to the reverse direction or from the reverse direction to the forward direction, the control signals VBD_(CLK) and XBD_(CLK) remain the same and only the phases of the clock signals CLK and XCLK changed.

FIG. 6 is a timing diagram of the shift register circuit 500 of the second embodiment of the present invention. As shown in FIG. 6, there is a phase difference D between the control signals VBD_(CLK) and XBD_(CLK) and the clock signals CLK and XCLK. The phase difference D is disposed for ensuring the sampling of the shift register from the input signals is valid. Assuming in the forward direction, each of the shift registers SR₁˜SR₃ respectively samples the input signals SRI₁₁˜SRI₃₁, at the falling edges of the clock signal CLK, each of the shift registers SR₁˜SR₃ respectively samples the input signals SRI₁₂˜SRI₃₂ at the rising edges of the clock signal XCLK for stopping outputting shift register signals SRO₁˜SRO₃. Thus, as for the shift register SR₁, when the start signal ST is input, the control signal VBD_(CLK) is at the low voltage (while the control signal XBD_(CLK) is at the high voltage), which turns on the switch unit CM₄₁, turns off the switch unit CM₄₂, and thus the start signal ST is served as the input signal SRI₁₁; when the shift register signal SRO₂ is input, the control signal XBD_(CLK) is at the low voltage (while the control signal VBD_(CLK) is at the high voltage), which turns on the switch unit CM₄₃, turns off the switch unit CM₄₄, and thus the shift register signal SRO₂ is served as the input signal SRI₁₂. As for the shift register SR₂, when the shift register signal SRO₁ is input, the control signal XBD_(CLK) is at the low voltage (while the control signal VBD_(CLK) is at the high voltage), which turns on the switch unit CM₅₁, turns off the switch unit CM₅₂, and thus the shift register signal SRO₁ is served as the input signal SRI₂₁; when the shift register signal SRO₃ is input, the control signal VBD_(CLK) is at the low voltage (while the control signal XBD_(CLK) is at the high voltage), which turns on the switch unit CM₅₃, turns off the switch unit CM₅₄, and thus the shift register signal SRO₃ is served as the input signal SRI₂₂. As for the shift register SR₃, when the shift register signal SRO₂ is input, the control signal VBD_(CLK) is at the low voltage (while the control signal XBD_(CLK) is at the high voltage), which turns on the switch unit CM₆₁, turns off the switch unit CM₆₂, and thus the shift register signal SRO₂ is served as the input signal SRI₃₁; when the start signal ST is input, the control signal XBD_(CLK) is at the low voltage (while the control signal VBD_(CLK) is at the high voltage), which turns on the switch unit CM₆₃, turns off the switch unit CM₆₄, and thus the start signal ST is served as the input signal SRI₃₂. In this way, the transmission of the shift register signals in the forward direction is achieved by utilizing the phases of the clock signals CLK and XCLK. The operation of the transmission of the shift register signals in the reverse direction is similar and is omitted.

To sum up, the switch set of the bi-directional shift register circuit of the present invention utilizes clock signals as the control signals for the switches. Since the control signals of the switches do not always stay at same voltages in one direction, the aging problem of the switches is solved and therefore the lifespan of the switches increases.

While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

1. A switch set for use in a bi-directional shift register module, the shift register module comprising a first shift register, a second shift register, and a third shift register, the second shift register coupled to the first shift register, the third shift register coupled to the second shift register, the shift register module sequentially transmitting shift register signals according to a first clock signal and an inversed clock signal of the first clock signal, the switch set comprising: a first switch device, comprising: a first control end for receiving a second clock signal; a second control end for receiving an inversed clock signal of the second clock signal; a third control end for receiving the second clock signal; a first input end for receiving a start signal; a second input end coupled to an output end of the second shift register; a first output end coupled to an input end of the first shift register for coupling the first input end of the first switch device to the first input end of the first shift register when the second clock signal is at a first predetermined voltage; and a second output end coupled to the input end of the first shift register for coupling the second input end of the first switch device to the first input end of the first shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage; a second switch device, comprising: a first control end for receiving the inversed clock signal of the second clock signal; a second control end for receiving the second clock signal; a third control end for receiving the inversed clock signal of the second clock signal; a first input end for receiving the start signal; a second input end coupled to an output end of the second shift register; a first output end coupled to an second input end of the first shift register for coupling the first input end of the second switch device to the second input end of the first shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage; and a second output end coupled to the second input end of the first shift register for coupling the second input end of the second switch device to the second input end of the first shift register when the second clock signal is at the first predetermined voltage; a third switch device, comprising: a first control end for receiving the inversed clock signal of the second clock signal; a second control for receiving the second clock signal; a third control for receiving the inversed clock signal of the second clock signal; a first input end coupled to an output end of the first shift register; a second input end coupled to an output end of the third shift register; a first output end coupled to a first input end of the second shift register for coupling the first input end of the third switch device to the first input end of the second shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage; and a second output end coupled to the first input end of the second shift register for coupling the second input end of the third switch device to the first input end of the second shift register when the second clock signal is at the first predetermined voltage; and a fourth switch device, comprising: a first control end for receiving the second clock signal; a second control end for receiving the inversed clock signal of the second clock signal; a third control end for receiving the second clock signal; a first input end coupled to the output end of the first shift register; a second input end coupled to the output end of the third shift register; a first output end coupled to a second input end of the second shift register for coupling the first input end of the fourth switch device to the second end of the second shift register when the second clock signal is at the first predetermined voltage; and a second output end coupled to the second input end of the second shift register for coupling the second input end of the fourth switch device to the second input end of the second shift register when the inversed clock signal of the second clock signal is at the first predetermined voltage.
 2. The switch set of claim 1, wherein the first switch device comprises: a first switch unit, comprising: a first switch, comprising: a first end coupled to the first input end of the first switch device; a control end coupled to the first control end of the first switch device; and a second end coupled to the first output end of the first switch device for coupling to the first end of the first switch when the second clock signal is at the first predetermined voltage; and a second switch, comprising: a first end coupled to the first input end of the first switch device; a control end coupled to the second control end of the first switch device; and a second end coupled to the first output end of the first switch device for coupling to the first end of the second switch when the inversed clock signal of the second clock signal is at the first predetermined voltage; and a second switch unit, comprising: a third switch, comprising: a first end coupled to the second input end of the first switch device; a control end coupled to the second control end of the first switch device; and a second end coupled to the second output end of the first switch device for coupling to the first end of the third switch when the inversed clock signal of the second clock signal is at the first predetermined voltage; and a fourth switch, comprising: a first end coupled to the second input end of the first switch device; a control end coupled to the third control end of the first switch device; and a second end coupled to the second output end of the first switch device for coupling to the first end of the fourth switch when the second clock signal is at the first predetermined voltage.
 3. The switch set of claim 2, wherein the first and the third switches are PMOS, and the second and the fourth switches are NMOS.
 4. The switch set of claim 1, wherein when the shift register module is set to transmit in a first direction, first clock input ends of the first, second, and the third shift registers receive the first clock signal, and second clock input ends of the first, second, and the third shift registers receive an inversed clock signal of the first clock signal; when the shift register module is set to transmit in a reverse direction of the first direction, first clock input ends of the first, second, and the third shift registers receive the inversed clock signal of the first clock signal, and second clock input ends of the first, second, and the third shift registers receive the first clock signal.
 5. The switch set of claim 1, wherein frequencies of the first and the second clock signals are the same.
 6. The switch set of claim 1, wherein phases of the first and the second clock signals are different.
 7. The switch set of claim 4, wherein phases of the first and the second clock signals are the same.
 8. The switch set of claim 1, wherein duty cycle ratio of the second clock signal is adjustable. 